Implement Logical Expression MCQ Quiz - Objective Question with Answer for Implement Logical Expression - Download Free PDF

Concept:

In a 4 × 1 MUX

Truth-Table

Y = Output = S̅1 S̅0 I0 + S̅1 S0 I1 + S1 S̅0 I2 + S1 S0 I3

Analysis:

f = S̅₁ S̅₀ I₀ + S̅₁ S₀ I₁ + S₁ S̅₀ I₂ + S₁ S₀ I₃

= x̅ y̅ (1) + x̅ y (0) + x y̅ (0) + xy (1)

Concept:

• A multiplexer with n-data select inputs can implement any function of n-variables and some function of (n + 1) variables.
• The key to this design is to use the most significant input variable and its complement to drive some of the data inputs.

Calculation:

Given 16:1 MUX, i.e. 2⁴:1 MUX,

Here, we have 4 data select lines.

Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2ⁿ output lines. Therefore, Decoder - n lines to 2ⁿ lines

The multiplexer is a combinational logic circuit designed to switch 1 of several (2ⁿ) input lines to a single common output line. Therefore, Multiplexer - 2ⁿ lines to 1 line

A de-multiplexer is a device that takes 1 input line and routes it to one of several (2ⁿ) digital output lines. Therefore, De multiplexer - 1 line to 2ⁿ lines

Concept:

The number of select lines required for an N×1 multiplexer is log₂ N.

Calculation:

number of registers = 32. So, N = 32

Output of MUX:

Y = A′B′C + A′BC′ + AB′C′ + ABC

Y = (A ⊕ B ⊕ C)

Y = ∑(1,2,4,7), difference equation of full subtractor.

Truth table:

The output equation of MUX = Y = S_difference = S_sum

Therefore, multiplexer circuit is equivalent to sum equation of full adder as well as difference equation of a full subtractor

NOTE:

Since it is official ISRO CS 2020 question marks has been given for option 1 and option 4. 

.Original 4 is this. "Difference equation of a full subtractor"  which is changed to get correct answer

A(B + C) + AB + (A + B)C

= AB + AC + AB + AC + BC

Concept:

• A multiplexer with n-data select inputs can implement any function of n-variables and some function of (n + 1) variables.
• The key to this design is to use the most significant input variable and its complement to drive some of the data inputs.

Calculation:

Given 16:1 MUX, i.e. 2⁴:1 MUX,

Here, we have 4 data select lines.

input given at 0 is R̅ in MUX 2

Concept:

For a 2: 1 multiplexer, if S is enabled and I₀, I₁ are the input, output = S̅ I₀ + SI₁

Explanation:

                          MUX 1                       MUX 2

Here, output of MUX 1 is input to MUX 2.

Here, output of MUX1 = P̅.0 + P.R = P R

Output of MUX 2 = X = Q̅.R̅  + Q.P.R

The minimal sum of products form of the output X is Q̅.R̅ + PQR

Concept:

The number of select lines required for an N×1 multiplexer is log₂ N.

Calculation:

number of registers = 32. So, N = 32

Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2ⁿ output lines. Therefore, Decoder - n lines to 2ⁿ lines

The multiplexer is a combinational logic circuit designed to switch 1 of several (2ⁿ) input lines to a single common output line. Therefore, Multiplexer - 2ⁿ lines to 1 line

A de-multiplexer is a device that takes 1 input line and routes it to one of several (2ⁿ) digital output lines. Therefore, De multiplexer - 1 line to 2ⁿ lines

Output of MUX:

Y = A′B′C + A′BC′ + AB′C′ + ABC

Y = (A ⊕ B ⊕ C)

Y = ∑(1,2,4,7), difference equation of full subtractor.

Truth table:

The output equation of MUX = Y = S_difference = S_sum

Therefore, multiplexer circuit is equivalent to sum equation of full adder as well as difference equation of a full subtractor

NOTE:

Since it is official ISRO CS 2020 question marks has been given for option 1 and option 4. 

.Original 4 is this. "Difference equation of a full subtractor"  which is changed to get correct answer

A(B + C) + AB + (A + B)C

= AB + AC + AB + AC + BC

Concept:

• A multiplexer with n-data select inputs can implement any function of n-variables and some function of (n + 1) variables.
• The key to this design is to use the most significant input variable and its complement to drive some of the data inputs.

Calculation:

Given 16:1 MUX, i.e. 2⁴:1 MUX,

Here, we have 4 data select lines.

Data:

M = 64, N = 4

Fomula:

L ≥ log_NM

L = The number of levels of connection required.

Calculation:

$L\ge \frac{{\log }_{a}M}{{\log }_{\mathrm{a}}N}$

$L\ge \frac{{\log }_{a}64}{{\log }_{\mathrm{a}}4}$

∴ L ≥ 3

L_min = 3

∴ the minumum level required for 4 x 1 MUX = 3

Total number of MUX 4 × 1 is

$\frac{64}{4^1}+\frac{64}{4^2}+\frac{64}{4^3}=16+4+1=21$

Concept:

For a general 4 to 1 multiplier as shown, the output expression is written as:

F = S̅1S̅2I0 + S̅1S2I1 + S1S̅2I2 + S1S2I3  

i.e. I0 will be the output when the select inputs are 00, I1 will be the output when the select Inputs are 01, and so on.

Analysis:

$F=\overline{S_1}.\overline{S_2}.R+\overline{S_1}.S_2.\overline{R}+S_1.\overline{S_2}.0+S_1.S_2.1$

$F=\overline{S_1}.\overline{S_2}R+\overline{S_1}{S}_2\overline{R}+S_1{S}_2$

$F=\overline{x}.\overline{y}.R+\bar{x}y.\overline{R}+xy$

$F=\overline{x}.\overline{y}.R+y(x+\overline{x.}\overline{R})$

$F=\overline{x}.\overline{y}.R+y(x+\overline{R})$

$F=\overline{x}.\overline{y}.R+yx+y\overline{R}$

$F=yx+y.\overline{R}+\overline{y}\overline{x}.R$