Multiplexer MCQ Quiz - Objective Question with Answer for Multiplexer - Download Free PDF

Encoder:

An encoder has 2ⁿ input lines and n output lines. In the encoder, the output lines generate the binary code corresponding to the input value which is active high.

Decoder:

It is a multi-input and multi-output logic circuit that converts coded inputs into coded outputs where input and output codes are different. Input code has fewer bits than output code. There is one to one mapping from input to output.

Multiplexer:

It is a digital switch. It allows digital information from several sources to be routed onto a single output line. A basic multiplexer has several data input lines and a single output line. The selection of a particular input line is controlled by selection lines. It is many to one mapping and provides the digital equivalent of an analog selector switch. Therefore it is the correct answer

Demultiplexer:

It is a circuit that receives information on a single line and transmits information on one of the 2ⁿ output lines. Selection of output line is controlled by values of n selection lines. 

To implement 2n × 1 MUX using 2 × 1 MUX, the total number of 2 × 1 MUX required is (2n - 1).

∴ The number of 2 × 1 multiplexer required to implement 16 × 1 MUX will be:

n = 16 - 1 = 15

Or we can follow the below steps to calculate the same:

1st stage \(= \frac{{16}}{2} = 8\)

2nd  stage \(\; = \frac{8}{2} = 4\)

3rd stage \(= \frac{4}{2} = 2\)

4th stage \(= \frac{2}{2} = 1\)

The sum will give the total number of MUX required to implement 16 × 1 multiplexer using 2 × 1, i.e.

n = 8 + 4 + 2 + 1 = 15

To implement 2n × 1 MUX using 2 × 1 MUX, the total number of 2 × 1 MUX required is (2n - 1).

∴ The number of 2 × 1 multiplexer required to implement 16 × 1 MUX will be:

n = 16 - 1 = 15

Or we can follow the below steps to calculate the same:

1st stage \(= \frac{{16}}{2} = 8\)

2nd  stage \(\; = \frac{8}{2} = 4\)

3rd stage \(= \frac{4}{2} = 2\)

4th stage \(= \frac{2}{2} = 1\)

The sum will give the total number of MUX required to implement 16 × 1 multiplexer using 2 × 1, i.e.

n = 8 + 4 + 2 + 1 = 15

• A 4-to-1 multiplexer has 4 input lines, 1 output line, and 2 selection lines.

• To handle 32 inputs, group them into 8 sets of 4 inputs each (since 32÷4=8).
• Each group will require one 4-to-1 multiplexer to select one of the 4 inputs.
• Number of multiplexers needed at this stage: 8.

• The 8 outputs from the first stage now act as inputs to a second layer.
• These 8 outputs can be connected to 2 additional 4-to-1 multiplexers, as  8÷4=2.
• Number of multiplexers needed at this stage: 2
   

• The 2 outputs from the second layer are connected to a final 4-to-1 multiplexer to get the single output.
• Number of multiplexers needed at this stage: 1.

To implement 2n × 1 MUX using 2 × 1 MUX, the total number of 2 × 1 MUX required is (2n - 1).

∴ The number of 2 × 1 multiplexer required to implement 16 × 1 MUX will be:

n = 16 - 1 = 15

Or we can follow the below steps to calculate the same:

1st stage \(= \frac{{16}}{2} = 8\)

2nd  stage \(\; = \frac{8}{2} = 4\)

3rd stage \(= \frac{4}{2} = 2\)

4th stage \(= \frac{2}{2} = 1\)

The sum will give the total number of MUX required to implement 16 × 1 multiplexer using 2 × 1, i.e.

n = 8 + 4 + 2 + 1 = 15

Concept:

In a 4 × 1 MUX

Truth-Table is given as:

Y = Output = S̅1 S̅0 I0 + S̅1 S0 I1 + S1 S̅0 I2 + S1 S0 I3

MUX contains AND gate followed by OR gate

Calculation:

Given:

Z = Output = A̅B̅C + A̅BC + AB̅C̅ + ABC̅ 

Z = A̅C(B̅ + B) + AC̅(B̅ + B)

Z = A̅C + AC̅

Z = A XOR C

Hence, option 4 is correct.

The correct answer is option 2.

Concept:

In a 4 × 1 MUX

Truth-Table is given as:

Y = Output = S̅1 S̅0 I0 + S̅1 S0 I1 + S1 S̅0 I2 + S1 S0 I3

MUX contains AND gate followed by OR gate

Calculation:

Given:

Z = Output = P̅Q̅R + P̅QR̅ +PQ̅ R̅ + PQR

Z = P̅(Q̅R + QR̅ ) +P(Q̅ R̅ + QR)

Z = \(\overline P.\overline{(\bar QR +Q\bar R)} +P. {(\bar Q\bar R +QR) }\)

Z = P ⊙ Q ⊙ R = P ⊕ Q ⊕ R

Concept:

Multiplexer: 

• A multiplexer is Many to one data selector.
• A multiplexer selects one of the many data available at its input depending on the bits on the select line.
• For selecting eight inputs, there are three data select lines that must be used. The multiplexer requires the data select lines. We have three data select lines for eight inputs, and it's an 8:1 multiplexer.

Example:

The 16 × 1 multiplexer selects one of the 8 inputs and presents it to the output, i.e.
2m  = 16
m = log2 16 = log2 (2⁴)
m = 4log2 2
m = 4

So, the number of data select lines is 4.

Multiplexers:

• A multiplexer is a combinational circuit.
• A multiplexer is Many to one data selector.
• A multiplexer selects one of the many data available at its input depending on the bits on the select line.
• For 2n inputs, there are n select lines that determine, which input is to be connected to the output.

Example:

A 4-input multiplexer is as shown below.

Output, Y = I0S̅1S̅0 + I1S̅1S0 + I2S1S̅0 + I3S1S0

The output of a 4-input multiplexer represents one combinational functions of 3-variables each.

The function can be seen as a combination of AND-OR functions. (Sum of products)

Concept:

The number of selection line is n for n bit resistor in multiplexer:

No. selection line in MUX = log2 n

In the destination decoder,

No. of selection line = log2 n

Analysis:

Given:

Mux is 4 x 1

So, n = 4 

No. of the selection line in MUX = log2n 

No. of the selection line in decoder = log2 4 = 2 bit

Option (3) is the correct choice.

Important Points

More information about MUX:

1) It is a data selector combinational circuit.

2) It is many to-one, parallel to serial convertor

3) It is also called universal logic circuit

4) MUX contain AND gate followed by OR gate

A(B + C) + AB + (A + B)C

= AB + AC + AB + AC + BC

Concept:

• A multiplexer with n-data select inputs can implement any function of n-variables and some function of (n + 1) variables.
• The key to this design is to use the most significant input variable and its complement to drive some of the data inputs.

Calculation:

Given 16:1 MUX, i.e. 2⁴:1 MUX,

Here, we have 4 data select lines.

Set of inputs = {x, a, b}

Set of output = y

Also, the selection of a or b for output is dependent on value of x.

if x = 1, y = a

if x = 0, y = b

Hence, x acts as a selects the value. Therefore, this resembles a 2-to-1 MUX or 2-input Multiplexer.

The correct option is 1

Concept:

De-multiplexer:

• The demultiplexer is a combinational logic circuit designed to switch one common input line to one of several separate output lines.
• The data distributor, known as a Demultiplexer or “Demux”, works in just the opposite way to that of the Multiplexer.
• The demultiplexer takes one single input data line and then switches it to any one of several individual output lines one at a time.

The block diagram is as shown:

Application:

The de-multiplexer converts a serial data signal at the input to parallel data at its output lines as shown below.

The function of the De-multiplexer is to switch one common data input line to any one of the 4 output data lines A to D.

Important:

Multiplexer:

The multiplexer is a combinational logic circuit designed to switch one of several input lines to a single common output line.

• The multiplexer or “MUX” is a combinational logic circuit designed to switch one of several input lines through a single common output line by the application of a control signal.
• Multiplexers operate like very fast-acting multiple-position rotary switches connecting or controlling multiple input lines called “channels” one at a time to the output.
• Multiplexers are used to convert parallel to serial data.

Multiplexer:

• A multiplexer (MUX) is a combinational logic circuit designed to switch one of several inputs to a single common output line.
• A multiplexer is Many to One data selector
• A multiplexer selects one of the many data available at its input depending on the bits on the select line
• For 2n inputs, there are n select lines that determine, which input is to be connected to the output.

Example:

A 4-input multiplexer is as shown below.

Output, Y = I0S̅1S̅0 + I1S̅1S0 + I2S1S̅0 + I3S1S0

The output of 4-input multiplexer represents one combinational functions of 3-variables each.