Combinational Circuits MCQ Quiz - Objective Question with Answer for Combinational Circuits - Download Free PDF

Encoder:

An encoder has 2ⁿ input lines and n output lines. In the encoder, the output lines generate the binary code corresponding to the input value which is active high.

Decoder:

It is a multi-input and multi-output logic circuit that converts coded inputs into coded outputs where input and output codes are different. Input code has fewer bits than output code. There is one to one mapping from input to output.

Multiplexer:

It is a digital switch. It allows digital information from several sources to be routed onto a single output line. A basic multiplexer has several data input lines and a single output line. The selection of a particular input line is controlled by selection lines. It is many to one mapping and provides the digital equivalent of an analog selector switch. Therefore it is the correct answer

Demultiplexer:

It is a circuit that receives information on a single line and transmits information on one of the 2ⁿ output lines. Selection of output line is controlled by values of n selection lines. 

The correct option is 4

• For any given 3-bit input, the decoder activates exactly one output line corresponding to that input's binary value.
• All other outputs remain inactive (typically logic 0).

Concept:

• A decoder is a combinational logic constructed with logic gates.
• It is the reverse of the encoder.
• A decoder circuit is used to transform a set of digital input signals into an equivalent decimal code of its output. For ‘n’ inputs a decoder gives ‘2n’ outputs.
• Block diagram of the Decoder is shown below:

Explanation:

How many select lines are required for a 1-to-8 Demultiplexer?

 A demultiplexer, or demux, is a combinational logic circuit designed to take a single input line and route it to one of several output lines. The specific output line to which the input is routed is determined by the select lines. A 1-to-8 demultiplexer has one input, eight outputs, and a set of select lines that determine which output line the input is sent to.

8 = 2^m

To find m, we take the logarithm base 2 of both sides:

log₂(8) = m

Since 2³ = 8, we find that:

m = 3

Therefore, 3 select lines are required for a 1-to-8 demultiplexer.

Explanation:

1-to-4 Demultiplexer

Definition: A 1-to-4 demultiplexer is a digital switch that takes a single input and directs it to one of four outputs based on the values of two select lines (S1 and S0). It is used to distribute data from one input to one of several output lines.

Working Principle: The 1-to-4 demultiplexer works by using the values of the select lines to determine which output line will receive the input signal. The select lines (S1 and S0) are binary values that can represent one of four possible combinations (00, 01, 10, 11). Based on these combinations, the input is directed to the corresponding output.

Case Analysis:

• If S1 = 0 and S0 = 0, the input I is directed to Output 0.
• If S1 = 0 and S0 = 1, the input I is directed to Output 1.
• If S1 = 1 and S0 = 0, the input I is directed to Output 2.
• If S1 = 1 and S0 = 1, the input I is directed to Output 3.

Given the input conditions: I = 1, S1 = 1, and S0 = 0, we can analyze which output will be active.

Step-by-Step Solution:

1. Identify the binary combination of the select lines:

S1 = 1 and S0 = 0 corresponds to the binary combination "10".

2. Determine which output corresponds to the binary combination "10":

From the case analysis above, we know that the combination "10" directs the input to Output 2.

3. Apply the input to the determined output:

Since I = 1, Output 2 will receive the input signal and will be set to 1, while all other outputs will remain 0.

Therefore, the output values will be:

• Output 0 = 0
• Output 1 = 0
• Output 2 = 1
• Output 3 = 0

Correct Option: Option 4 (Output 0 = 0, Output 1 = 0, Output 2 = 1, Output 3 = 0)

The correct answer is: 1) Each full adder waits for the carry from the previous full adder.
Explanation:
A serial binary adder processes binary addition one bit at a time, sequentially propagating the carry from one stage to the next. Here’s why Option 1 is correct:

Characteristic of Serial Adders:

Sequential Carry Propagation: Each full adder (FA) must wait for the carry-out from the previous FA before computing its sum and carry.

Example: To compute bit *i*, the adder needs the carry generated from bit i−1.

Operates Bit-by-Bit: Unlike parallel adders, serial adders do not process all bits simultaneously.

Concept:

In a 4 × 1 MUX

Truth-Table is given as:

Y = Output = S̅1 S̅0 I0 + S̅1 S0 I1 + S1 S̅0 I2 + S1 S0 I3

MUX contains AND gate followed by OR gate

Calculation:

Given:

Z = Output = A̅B̅C + A̅BC + AB̅C̅ + ABC̅ 

Z = A̅C(B̅ + B) + AC̅(B̅ + B)

Z = A̅C + AC̅

Z = A XOR C

Hence, option 4 is correct.

The major steps involved in PCM are sampling, quantizing, and encoding.

Encoder:

• An encoder performs the conversion of the quantized signal into binary codes.
• This unit generates a digitally encoded signal which is a sequence of binary pulses that acts as the modulated output.
• It is a binary encoder thus generates a binary code sequence. That is transmitted through the transmission path.
• The encoder is a combinational logic circuit that converts an active input signal into a coded output signal.
• It has n input lines, only one of which is active at any time, and m output lines.
• It encodes one of the active inputs to a coded binary output with m bits.
• In an encoder, the number of output lines is less than the number of inputs.
• If an encoder has n input lines and m output lines then n<= 2m.

The correct answer is option 2.

Concept:

In a 4 × 1 MUX

Truth-Table is given as:

Y = Output = S̅1 S̅0 I0 + S̅1 S0 I1 + S1 S̅0 I2 + S1 S0 I3

MUX contains AND gate followed by OR gate

Calculation:

Given:

Z = Output = P̅Q̅R + P̅QR̅ +PQ̅ R̅ + PQR

Z = P̅(Q̅R + QR̅ ) +P(Q̅ R̅ + QR)

Z = \(\overline P.\overline{(\bar QR +Q\bar R)} +P. {(\bar Q\bar R +QR) }\)

Z = P ⊙ Q ⊙ R = P ⊕ Q ⊕ R

Truth Table for half substractor:

\( Difference = A⊕B = A\bar B + \bar AB \)

\(Borrow = X=\bar AB\)

Concept:

A decoder with k input lines has 2^k output lines.

Calculation:

The memory is byte-addressable. So 1 KB = 2¹⁰ B.

10 × 2¹⁰ decoders.

So, the number of input lines (m) = 10

Number of output lines (n) = 2^m = 2¹⁰ = 1024

Hence, (m + n) = 10 + 1024 = 1034 

Formula:

The total time taken by the for ‘n’ bit ripple carry adder is

T_d = (n – 1) t_c + Maximum(t_c, t_s)

t_c = delay for carry through a single flip flop.

t_{s =} delay for sum

Data:

Each full adder takes 34 ns for computing

From this, Maximum(t_c, t_s) = t_s = 34 ns

T_d = 90 ns.

n = 8

Calculation:

T_d = (n – 1) t_c + Maximum(t_c, t_s)

90 = (8 – 1)t_c + 34

7tc = 56 ns.

∴tc = 8 ns.

Time taken by each full adder to find carry is 8 ns.

Hence, the correct answer is option 4.

Concept:

Multiplexer: 

• A multiplexer is Many to one data selector.
• A multiplexer selects one of the many data available at its input depending on the bits on the select line.
• For selecting eight inputs, there are three data select lines that must be used. The multiplexer requires the data select lines. We have three data select lines for eight inputs, and it's an 8:1 multiplexer.

Example:

The 16 × 1 multiplexer selects one of the 8 inputs and presents it to the output, i.e.
2m  = 16
m = log2 16 = log2 (2⁴)
m = 4log2 2
m = 4

So, the number of data select lines is 4.

Multiplexers:

• A multiplexer is a combinational circuit.
• A multiplexer is Many to one data selector.
• A multiplexer selects one of the many data available at its input depending on the bits on the select line.
• For 2n inputs, there are n select lines that determine, which input is to be connected to the output.

Example:

A 4-input multiplexer is as shown below.

Output, Y = I0S̅1S̅0 + I1S̅1S0 + I2S1S̅0 + I3S1S0

The output of a 4-input multiplexer represents one combinational functions of 3-variables each.

The function can be seen as a combination of AND-OR functions. (Sum of products)

Concept:

The number of selection line is n for n bit resistor in multiplexer:

No. selection line in MUX = log2 n

In the destination decoder,

No. of selection line = log2 n

Analysis:

Given:

Mux is 4 x 1

So, n = 4 

No. of the selection line in MUX = log2n 

No. of the selection line in decoder = log2 4 = 2 bit

Option (3) is the correct choice.

Important Points

More information about MUX:

1) It is a data selector combinational circuit.

2) It is many to-one, parallel to serial convertor

3) It is also called universal logic circuit

4) MUX contain AND gate followed by OR gate

A(B + C) + AB + (A + B)C

= AB + AC + AB + AC + BC