Question
Download Solution PDFWhat is one disadvantage of an S-R flip-flop ?
Answer (Detailed Solution Below)
Detailed Solution
Download Solution PDFAn unclocked R-S flip flop using NOR gates is as shown:
The truth table for the circuit is shown:
|
S |
R |
Q+ |
|
0 |
0 |
Q (no change) |
|
0 |
1 |
0 (Reset) |
|
1 |
0 |
1 (set) |
|
1 |
1 |
Invalid/Forbidden state |
When the S and R inputs of an SR flipflop are at logical 1, then the output becomes unstable and it is known as a race condition.
So, the main disadvantage of the SR flip flop is invalid output when both inputs are high.
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