Question
Download Solution PDFIn the following sequential circuit, the sequence followed by A and B on rising edge of CLK after reset is de-asserted is
Answer (Detailed Solution Below)
Detailed Solution
Download Solution PDFDuring t0 all Q values are set to zero,
Hence \(D = A \oplus B = 1\)
And\(\;A = {\bar Q_2};B = {Q_1}\)
During raising edge Q1 = previous value of D i.e. 1 and Q2 is equal to previous value of Q1 i.e. 0 (10)
⇒ Present state D = 1 ⊕ 1 = 0
Similarly for next clock pulse Q1 = 0 and Q2 = 1 ⇒ D = 0 (01)
For next pulse Q1 =0 Q2 = 0 ⇒ D = 1 which is initial state (00)
Hence Sequence followed is 10, 01, 00, 10……Last updated on Apr 11, 2023
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