Adder MCQ Quiz in मल्याळम - Objective Question with Answer for Adder - സൗജന്യ PDF ഡൗൺലോഡ് ചെയ്യുക

Concept:

Longest latency for the sum to stabilize is the maximum time or delay a ripple carry adder take to add A and B.

Explanation:

Given A = 1 in decimal form,

In 2’s complement form, binary representation of A in binary form = 0000 0001.

In case of ripple carry adder, for sum we need 2 XOR gates.

For the longest latency, we must have C_in = 1 at every stage of the ripple carry adder.

Here, we have to find the value of B such that we get C_in= 1 at every stage and C_out = 1 at the last stage.

Maximum delay is when we take B = -1 in decimal (1111 1111 – in binary)

half Adder

Full Addere using 2 half adder and OR gate

Hence processing delay is 4.8, given all the bits are added by full adder, total processing delay will be 4 × 4.8 = 19.2

Also first bit could be added using half adder in that case processing delay will be 16.8

Concept:

Half adder circuit have two inputs and two outputs (sum and carry).

Sum (S) = A⊕B, Carry = A.B

Full Adder:

A digital circuit that performs addition is called a full adder. Hardware implements full adders using logic gates. Three one-bit binary values, two operands, and a carry bit are added using a complete adder. Two numbers are output by the adder: a sum and a carry bit. When compared to a half adder, which adds two binary digits, the term is used.

Explanation:

The adder known as a "full adder" adds three inputs and generates two outputs. A and B make up the first two inputs, and C-IN is the third input. The normal output is denoted as S, which represents SUM, while the output carry is designated as C-OUT.

The truth table of a full adder logic is:

The Sum output bit of a full adder is given by:

S = A ⊕ B ⊕ C

The carry output bit of a full adder is given by:

X1 = AB + BC + AC

Example: 3 bit carry adder:

C₁ = G₀ + P₀C₀ → 1 AND gate

C₂ = G₁ + P₁C₁ 

=G₁ + (G0 + P0C0 ) C1

= G1 + G0C1+ P0C0 C1 → 2 AND gate

C3 = G₂ + P₂C₂ 

=G2 + (G1 + G0C1+ P0C0 C1) C₂

= G2C2 + G1C2 + G0C1C2 + P0C0 C1 C2 → 3 AND gate

∴ number of gates = 1 + 2 + 3 = 6

Shortcut:

The number of AND gates required in carry circuit for n-bit look ahead carry adder is given by \(n(n+1) \over 2\)

Therefore, number of AND gates = \(\frac{10(10+1)}{2} = 55\)

Important Point:

FAN IN of AND gate is more than 2

In position 1 ground is connected

C_in = 0 (Ground is used)

Bin = (B₁C̅_in+ B̅₁C_in)(B0C̅in+ B̅0Cin)

Bin = (B₁0̅  + B̅₁0)(B00̅  + B̅o0)

B_in = B₁ B₀ = B (B₀ is LSB)

Similiarly A_in

A_in = A₁ A₀ = A

Since it is a full adder

S = A_in + B_in+ C_in = A + B + 0

∴ S = A + B

Example: 3 bit carry adder:

C₁ = G₀ + P₀C₀ → 1 AND gate

C₂ = G₁ + P₁C₁ 

=G₁ + (G0 + P0C0 ) C1

= G1 + G0C1+ P0C0 C1 → 2 AND gate

C3 = G₂ + P₂C₂ 

=G2 + (G1 + G0C1+ P0C0 C1) C₂

= G2C2 + G1C2 + G0C1C2 + P0C0 C1 C2 → 3 AND gate

∴ number of gates = 1 + 2 + 3 = 6

Shortcut:

The number of AND gates required in carry circuit for n-bit look ahead carry adder is given by \(n(n+1) \over 2\)

Therefore, number of AND gates = \(\frac{10(10+1)}{2} = 55\)

Important Point:

FAN IN of AND gate is more than 2

• Carry lookahead adders (CLAs) are indeed a method used in digital circuit design to speed up the process of adding binary numbers. Traditional ripple-carry adders have a delay associated with each stage, as the carry must propagate from one stage to the next, leading to longer overall addition times, especially for large numbers.
• CLAs minimize this delay by precomputing the carry signals for each stage based on the input values. This precomputation is done in parallel, allowing the carries to be generated simultaneously for all stages. As a result, the carry propagation time is greatly reduced, leading to faster addition operations.
• CLAs are often used in high-speed arithmetic circuits where fast addition is crucial, such as in processors and digital signal processing (DSP) applications. They offer improved performance compared to ripple-carry adders, especially for larger bit-width additions.
   

Additional Information 

CD40181:  It is a low-power four-bit parallel arithmetic logic unit (ALU) capable of providing 16 binary arithmetic operations.

CD40182: It is a high-speed look-ahead carry generator capable of anticipating a carry across four binary adders or groups of adders.

CD4527: It is a BCD rate multiplier (DRM) in a 16-lead DIP type package that provides an output pulse rate based upon the BCD input number.

CD4585: It is a 4-bit magnitude comparator designed for use in computer and logic applications that require the comparison of two 4-bit words.

The correct answer is Add the carry to the least significant bit (LSB)

Key Points

When you add binary numbers and there is a carry-out from the MSB, you incorporate this carry by adding it to the LSB to ensure the additional bit is accounted for in the result.

Example:
Adding the binary numbers 1011 (11 in decimal) and 1001 (9 in decimal):

Perform the initial addition:

   1011
+ 1001
 10100 (Binary result indicating carry-out)

Identify and add the carry to the LSB:

   10100 (Initial sum with carry-out)
    +     1 (Carry added to LSB)
   10101 (Corrected result)
Therefore, the sum is 10101 (21 in decimal). This method ensures that extra carry is properly added into the final result.

Based on this understanding, option 2 (Add the carry to the least significant bit (LSB)) is correctly chosen for this specific context and procedure.

Concept:

Half Adder :

The Half Adder is a type of combinational logic circuit that adds two of the 1-bit binary digits. It generates carry and sum of both the inputs.

Truth Table of Half Adder:

K-map for output variable Sum:

Sum= \(\bar AB+A \bar B\) = A⊕B =A EXOR B

Carry = AB

Full Adder:

The Full Adder is also a type of combinational logic that adds three of the 1-bit binary digits for performing an addition operation. It generates a sum of all three inputs along with a carry value.

Truth Table of Half Adder:

K-map for output variable Sum:

Formula:

For n-bit addition

The number of half adders needed  = 2×(n-1) + 1 

Calculation:

n=5