Question
Download Solution PDFMatch List-I with List-II and select the correct answer using the code given below the lists:
List-I | List-II |
a. Pipelined ALU | i. RISC |
b. Simpler compiler | ii. CISC |
c. Separate data and instruction caches |
iii. Mixed RISC-CISC |
d. Lesser cycles per instruction |
Answer (Detailed Solution Below)
Detailed Solution
Download Solution PDFConcept:
RISC [Reduced Instruction set computing] |
CISC [Complex instruction set computing] |
More no. of register require |
Less no. of register compare to RISC |
Lesser addressing mode present |
Higher addressing mode present |
Lesser cycle per instruction required |
Higher cycle per instruction required |
Instruction size is fix |
Instruction size is variable |
Hardwired control unit used |
μ programmed control unit is used |
Less no. of instruction required |
More no. of instruction required |
Note:
Pipelined ALU & separate date and instruction caches present in both i.e. RISC & CISC.
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