Instruction Pipelining MCQ Quiz - Objective Question with Answer for Instruction Pipelining - Download Free PDF
Last updated on Jun 26, 2025
Latest Instruction Pipelining MCQ Objective Questions
Instruction Pipelining Question 1:
What will the following instruction do?
INC EBX
Answer (Detailed Solution Below)
Instruction Pipelining Question 1 Detailed Solution
The correct answer is Option 4) Increment value in 32-bit register.
Key Points
INC
is an assembly language instruction that increases the value of a register or memory location by 1.EBX
is a 32-bit general-purpose register in the x86 architecture.INC EBX
increments the current 32-bit value stored in theEBX
register by 1.- This is commonly used in loop counters or arithmetic operations within low-level programming.
Additional Information
- Option 1 – Incorrect: There is no syntax error in
INC EBX
; it's a valid assembly instruction. - Option 2 – Partially Correct: It’s true that it increments the value in
EBX
, but the option lacks clarity about register size. - Option 3 – Incorrect:
EBX
is a 32-bit register, not an 8-bit one. The 8-bit part would beBL
. - Related Registers:
AX, BX, CX, DX
– 16-bit registersAL, BL, CL, DL
– 8-bit lower halvesEAX, EBX, ECX, EDX
– 32-bit registersRAX, RBX, RCX, RDX
– 64-bit registers (x86-64 architecture)
Instruction Pipelining Question 2:
For which of the following operations Arithmetic Pipeline would be used?
Answer (Detailed Solution Below)
Instruction Pipelining Question 2 Detailed Solution
The correct answer is Option 2) Floating-point operations.
Key Points
- Arithmetic pipelines are specialized pipelines designed to perform complex arithmetic computations efficiently by breaking them into multiple stages.
- They are especially useful for floating-point operations such as addition, subtraction, multiplication, and division.
- These operations involve multiple steps (e.g., alignment, normalization, rounding) that can be pipelined to improve performance.
- Each stage of the pipeline handles a part of the floating-point computation, allowing overlapping execution of multiple operations.
- This enhances the throughput of floating-point arithmetic, making it ideal for scientific and engineering applications.
Additional Information
- Option 1 – Incorrect: Popping a value from a stack is a simple memory operation, not arithmetic in nature.
- Option 3 – Incorrect: Integer operations are generally simpler and do not typically require pipelining due to fewer computation stages.
- Option 4 – Incorrect: Pushing values onto a stack is a memory access operation, unrelated to arithmetic pipelines.
- Example Use Cases of Arithmetic Pipelines:
- Graphics processing
- Scientific simulations
- Signal processing
- Mathematical co-processors in CPUs
Instruction Pipelining Question 3:
Which of the following is INCORRECT about an instruction Pipeline?
Answer (Detailed Solution Below)
Instruction Pipelining Question 3 Detailed Solution
The correct answer is Option 2) It is useful for performing floating point operations.
Key Points
- Instruction pipelining is a technique used in CPUs to improve instruction throughput by overlapping different stages (Fetch, Decode, Execute, etc.) of multiple instructions.
- It is mainly used for general instruction execution, not specifically for floating point operations, which are handled separately in the floating point unit (FPU).
- Floating point operations often involve more complex logic and longer latency; hence, they require specialized handling, not the standard instruction pipeline.
- This makes option 2 incorrect, as it misrepresents the primary purpose of instruction pipelining.
Additional Information
- Option 1 – Correct: Pipelining increases the throughput by allowing multiple instructions to be processed simultaneously at different stages.
- Option 3 – Correct: It enables overlapping of fetch, decode, and execute cycles — thus improving instruction flow.
- Option 4 – Correct: Pipelining allows the system to fetch new instructions from memory while previous ones are still being executed, utilizing different CPU segments concurrently.
- Common Pipeline Stages:
- Instruction Fetch (IF)
- Instruction Decode (ID)
- Execute (EX)
- Memory Access (MEM)
- Write Back (WB)
- Limitation: Pipelining does not eliminate data hazards, control hazards, or structural hazards — these must be managed via techniques like forwarding, stalls, and branch prediction.
Instruction Pipelining Question 4:
Consider the following sequence of micro operations :
MBR ← PC
MAR ← X
PC ← Y
MEMORY ← MBR
Which one of the following is possible operation performed by this sequence ?
Answer (Detailed Solution Below)
Instruction Pipelining Question 4 Detailed Solution
Correct Answer: Option 4) Initiation of interrupt service
Key Points
Let's examine the steps one by one:
- MBR ← PC:
- The content of the Program Counter (PC), which holds the address of the next instruction to be executed, is copied to the Memory Buffer Register (MBR).
- This is typically done to save the return address before jumping to an interrupt service routine (ISR).
- MAR ← X:
- The Memory Address Register (MAR) is loaded with the address X.
- This is the location where the return address (in MBR) will be stored.
- PC ← Y:
- The Program Counter is updated to Y, which points to the start of the ISR.
- This redirect of the control flow to a new memory location is characteristic of interrupt handling.
- MEMORY ← MBR:
- The value in the MBR (the original PC value) is stored in memory at the address specified by MAR (which is X).
- This effectively saves the return address so that the CPU can resume the original program after servicing the interrupt.
Therefore, this sequence of micro-operations matches the typical behavior during the initiation of an interrupt service routine, where:
- The current execution state (PC) is saved,
- The PC is redirected to the ISR location.
Final Answer: Option 4) Initiation of interrupt service
Instruction Pipelining Question 5:
Correct the order of instruction cycle:
A. Read the effective address
B. Fetch the information
C. Execute the instruction
D. Decode the instruction
Choose the correct answer from the options given below:
Answer (Detailed Solution Below)
Instruction Pipelining Question 5 Detailed Solution
The correct answer is Option 2: B, D, A, C.
Key Points
- The instruction cycle is the process by which a computer retrieves, decodes, and executes an instruction.
- The correct sequence of operations is:
- Fetch the information (B): The instruction is fetched from memory.
- Decode the instruction (D): The fetched instruction is decoded to understand the operation to be performed.
- Read the effective address (A): The effective address of the data required for the operation is determined.
- Execute the instruction (C): The instruction is executed and the desired operation is performed.
Additional Information
- The instruction cycle is fundamental to the operation of all computers and involves multiple steps to ensure that the correct operations are performed accurately.
- Each step in the cycle is crucial for the correct execution of instructions, ensuring that the computer processes data efficiently.
- Understanding the instruction cycle is important for those studying computer architecture and assembly language programming.
Top Instruction Pipelining MCQ Objective Questions
In microprocessors, the IC (instruction cycle), FC (fetch cycle) and EC (execution cycle) are related as
Answer (Detailed Solution Below)
Instruction Pipelining Question 6 Detailed Solution
Download Solution PDF- The Steps required by the CPU to fetch and execute an Instruction is called an instruction cycle. It consists of fetch and executes cycle.
- Instruction cycle (IC) = Fetch cycle (FC) + Execution cycle (EC)
- The time required by the microprocessor to complete the operation of accessing memory or I/O devices is called a machine cycle.
- Clock time is a known time state. It is reciprocal of clock frequency.
- Instruction cycle > Machine cycle > Clock cycle (time state)
Steps in the instruction cycle:
- First of all, the opcode is fetched by the microprocessor from a stored memory location.
- Then it is decoded by the microprocessor to find out which operation it needs to perform.
- If an instruction contains data or operand address which is still in the memory, the CPU has to perform read operation to get the desired data.
- After receiving the data, it performs to execute the operation.
Correct sequence: fetch → decode → read effective address → execute
Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure.
What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?
Answer (Detailed Solution Below)
Instruction Pipelining Question 7 Detailed Solution
Download Solution PDFThe correct answer is option 2
Concept:
The segments are separated by registers Ri that holds the intermediate results between the stages.
Data:
Stage delay and corresponding register delay given
S1 = 5 ,
S2 = 6 ,
S3 = 11,
S4 = 8,
And corresponding register delay is 1 for each stage
Number of stage = 4
Explanation:
Time is taken to execute N instructions in non-pipelined implementation will be =(5+6+11+8)N = 30×N
Clock period for pipelined implementation =max(5,6,11,8) + 1 = 12 ns
Time is taken to execute N instructions in pipelined implementation will be = (4 + N-1)12 ≈ 12×N (N is very large)
Speedup =
A non-pipelined CPU has 12 general purpose registers (R0, R1, R2,….R12). Following operations are supported
ADD Ra, Rb, Rr Add Ra to Rb and store the result in Rr
MUL Ra, Rb, Rr Multiply Ra to Rb and store the result in Rr
MUL operations takes two clock cycles, ADD takes one clock cycle.
Calculate minimum number of clock cycles required to compute the value of the expression XY + XYZ + YZ. The variables X, Y, Z are initially available in registers R0, R1 and R2 and contents of these registers must not be modified.Answer (Detailed Solution Below)
Instruction Pipelining Question 8 Detailed Solution
Download Solution PDFConcept -
XY + XYZ + YZ = (X × Y) + (X × Y × Z) + (Y × Z) = (X × Y) + (X × Y + Y) × Z
The instructions are non-pipelined and cycles for each instruction is mentioned. Therefore,
X × Y - takes 2 cycles
X × Y + Y - takes 1 cycles (X × Y already done)
(X × Y + Y) × Z - takes 2 cycles
(X × Y) + (X × Y + Y) × Z - takes 1 cycle
Hence, total cycles = 2 + 1 + 2 + 1 = 6
Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is _____.
Answer (Detailed Solution Below) 2.15 - 2.18
Instruction Pipelining Question 9 Detailed Solution
Download Solution PDFData:
For a non-pipelined processor,
Clock cycles to complete one instruction = 5
Instruction operating frequency = 2.5 GHz
One clock cycle time = 1/ (2.5 GHz) = 0.4 ns
For N number of instructions, clock cycles required = 5N
Time taken to complete 5n clock cycles = 0.4*5n = 2N ns
For a pipelined processor,
Stages of pipeline = 5
Overheads associated = 2 GHz
One clock cycle time = 1/ (2 GHz) = 0.5 ns
For n instructions, clock cycles required
Instruction type |
Number of such instructions |
% causing stalls |
Number of clock cycles |
Memory |
0.3N |
5% of 0.3N |
50 |
ALU |
0.6N |
None |
0 |
Branch |
0.1N |
50% of 0.1N |
2 |
Therefore, time taken by pipelined processor:
0.6N (1) + 0.3N [0.05 (1 + 50) + 0.95 (1)] + 0.1N [0.5 (1 + 2) + 0.5 (1)] cycles
= 1.85N cycles
= 1.85N/2 ns
= 0.925N ns
Speedup =
Consider a 5-segment pipeline with a clock cycle time 20ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute 100 instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline)
Answer (Detailed Solution Below)
Instruction Pipelining Question 10 Detailed Solution
Download Solution PDFData:
No. of pipeline segments = stages in pipeline, n = 5
Clock cycle time per operation = clock cycle per stage = 20 ns
No. of instructions = 100
Formula:
Calculation:
Twithout pipeline = no. of instructions × stages in pipeline × clock cycle per stage
= 100 × 5 × 20
Twith pipeline = (time for pipelined execution without stalls) + (overhead due to stalls)
= (5 + 99) × 20 + 20 × 20 = 124 × 20
Explanation:
→ For calculating the time for pipelined execution without stalls, it is considered that 1st instruction takes up an entire clock cycle, while each instruction after that takes up only the maximum time from all the segments. In our case, all the segments took an equal time of 20ns (1 Clock) hence,
time for pipelined execution without stalls = time required for first instruction + (n - 1) instructions taking 20 ns each = 5 × 20 + (100 - 1) × 20, that is we needed 104 clocks for complete execution
→ Overhead is calculated because it is mentioned in the question that every five cycles, a bubble due to data hazard has to be introduced in the pipeline. Hence ⌊ 104/5 ⌋ = 20 such overheads, each requiring 20ns of service time = 20 × 20The first machine cycle of an instruction is always a
Answer (Detailed Solution Below)
Instruction Pipelining Question 11 Detailed Solution
Download Solution PDFMachine Cycle: Time taken to execute one OPERATION is known as a machine cycle. One instruction will contain 1 to 5 machine cycles.
T-State: The portion of a machine cycle executed in one internal clock pulse is known as T-state.
Steps in the instruction cycle:
- First of all, the opcode is fetched by the microprocessor from a stored memory location.
- Then it is decoded by the microprocessor to find out which operation it needs to perform.
- If an instruction contains data or operand address which is still in the memory, the CPU has to perform read operation to get the desired data.
- After receiving the data, it performs to execute the operation.
Correct sequence: fetch → decode → read effective address → execute
Pipelining increases ______ of the processor.
Answer (Detailed Solution Below)
Instruction Pipelining Question 12 Detailed Solution
Download Solution PDFConcept:
Pipelining is an implementation technique whereby multiple instructions are overlapped in execution. It is like an assembly line.
Explanation:
In pipelining, each step operates parallel with other steps. It stores and executes instructions in an orderly manner.
The main advantages of using pipeline are :
- It increases the overall instruction throughput.
- Pipeline is divided into stages and stages are connected to form a pipe-like structure.
- We can execute multiple instructions simultaneously.
- It makes the system reliable.
- It increases the program speed.
- It reduces the overall execution time but does not reduce the individual instruction time.
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards.
The number of clock cycles required for completion of execution of the sequence of instructions is ______.
Answer (Detailed Solution Below) 219
Instruction Pipelining Question 13 Detailed Solution
Download Solution PDFTotal Instruction = 100
Instruction Fetch, Instruction Decode, Operand Fetch, and Writeback (WB) performed in 1 cycle.
PO stage:
40 instructions take 3 cycle
35 instructions take 2 cycles
25 instructions take 1 cycle
Average number of cycles = (40*3+35*2+25*1)/100 = 2.15 cycles.
On an average first instruction completed in 1+1+1+1+2.15 cycles
Remaining 99 instruction will takes 99*2.15 = 212.85 cycle
Total number of cycles is 6.15+212.85 = 219 cycles.
A non-pipeline system takes 50ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of 10ns. Determine approximately the speedup ratio of the pipeline for 500 tasks.
Answer (Detailed Solution Below)
Instruction Pipelining Question 14 Detailed Solution
Download Solution PDFConcept:
Speed up factor is defined as the ratio of time required for non-pipelined execution to that of time received for pipelined execution.
Data:
Time for non-pipelined execution per task = tn = 50 ns
Time for pipelined execution per task = tp = 10 ns
Number of stages in the pipeline = k = 6
Number of tasks = 500
Formula
S = speed up factor
Calculation:
Time for non-pipelined = Tn = tn × Number of tasks
Time for non-pipelined = Tn = 50 × 500
Time for pipelined = Tp = 1st task × k × tp + (All Remaining Tasks (k - 1)) × tp
Time for pipelined = Tp = 1 × 6 × 10 + (500 - 1) × 10
A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each.
The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is ______ nanoseconds.
Answer (Detailed Solution Below) 17160
Instruction Pipelining Question 15 Detailed Solution
Download Solution PDFData:
Number of Instructions = n = 100
Number of stages = 5;
Stage delay = 5 ns
Calculation:
Time taken by five stage pipeline processor of singel instruction = T = Max (150, 120, 150, 160,140) + stages delay
= 160 + 5 = 165 ns
The time required to execute n instructions with pipeline = [k + (n – 1)]T
= (5 + (100 - 1))×165 = 17160 ns