Successive Approx ADC MCQ Quiz in தமிழ் - Objective Question with Answer for Successive Approx ADC - இலவச PDF ஐப் பதிவிறக்கவும்

A 6-bit AC operation using a DAC step size of 40 mV is as shown below:

At t = t₀, set MSB (bit Q₅)

Register output = 100000₂ = 32₁₀

∴ V_AX = (40 mV) × 32 = 1.28 V

Comparing V_AX with V_A, V_AX remains constant for a set bit (Q₅ = 1).

At t = t₁, set Bit Q₄

Register output = 110000₂ = 48₁₀

∴ V_AX = (40 mV) × 48 = 1.92 V

After comparing V_AX with V_A, V_AX becomes 1.28 V, i.e. bit Q₄ becomes reset (Q₃ = 0)

At t = t₂, set Bit Q₃

Register output = 101000₂ = 40₁₀

∴ V_AX = (40 mV) × 40 = 1.6 V

After comparing V_AX with V_A, V_AX becomes 1.28 V, i.e. bit Q₃ becomes reset (Q₃ = 0)

At t = t₃, set bit Q₂

∴ The register output = 100100₂ = 36₁₀

∴ V_AX = (40 mA) × 36 = 1.44 V

After comparison of V_AX with V_A, V_AX becomes 1.44 V, i.e. bit Q₁ becomes reset (Q₁ = 0)

At t = t₄, set bit Q₁

Register output = 10010₂ = 38₁₀

∴ V_AX  = (40 mV) × 38 = 1.52 V

On comparing V_AX with V_A, V_AX becomes 1.44 V, i.e. bit Q₁ becomes reset (Q₁ = 0)

At t = t₅, set bit Q₀ (LSB)

Register output = 100101₂ = 37₁₀

∴ V_AX  = (40 mV) × 37 = 1.48 V

On comparing V_AX with V_A, V_AX remains constant for set bit Q₀ (Q₀ = 1)

∴ The resultant digital output is:

Q₅Q₄Q₃Q₂Q₁Q₀ = 100101₂

Input voltage = 8.15 V

Full scale value = 15 V

Number of bits = 4

Step size \(= \frac{{{V_{FSD}}}}{{{2^n} - 1}} = \frac{{15}}{{15}} = 1\;V.\)

First MSB is set to 1.

V_ref = (1000)₂ = 8

V_ref < V_in

Now, next higher bit is set to 1.

V_ref = (1100)₂ = 12

V_ref > V_in

As it is greater than V_in, bit will reset.

V_ref = (1000)₂ = 8

Now, next higher bit is set to 1.

V_ref = (1010)₂ = 10

V_ref > V_in ⇒ bit will reset.

V_ref = (1000)₂ = 8

Now, next higher bit is set to 1.

V_ref = (1001)₂ = 9

V_ref > V_in ⇒ bit will reset.

V_ref = (1000)₂.

So sequence of operation is

Flash ADC → Fastest, takes 1 clock cycle to convert

Counting type → Conversion time is α magnitude of input signal.

Integrating type → Also known as dual slope is slowest

Successive approximation type → In this ADC the time takes is n clock pulses (n is number of bits)

In practical cases the time taken is n+2 clock pulses

Maximum peak to peak ripple voltage = step size of ADC

% max quantization error \( = \pm \frac{1}{2} \times \% \) Resolution

\( = \pm \frac{1}{2} \times \frac{1}{{\left( {{2^8} - 1} \right)}} \times 100\)

\( = \pm \frac{1}{2} \times \frac{1}{{\left( {{2^8} - 1} \right)}} \times 100\)

In a n-bit  flash ADC \({2^n} - 1\) comparisons are made with respective voltage levels. Therefore, it requires \({2^n} - 1\) comparators.

Counter type ADC uses  linear search where as successive approximation ADC Uses Binary search

i) n-Bit flash ADC:-

• no. of comparators required = 2ⁿ – 1
• It is the fastest ADC.
• Its conversion time is = 1. Tclk

Successive Approximation Register ADC → (n Bit)

→ It uses Binary search for conversion.

→ Its conversion time = n tak

→ Its conversion time is independent of A mplitude of analog signal.

Counter type ADC:-

It uses linear search for conversion.

Conversion time = 2ⁿ – 1 (Tak)

Important Point-

Linear search-It is a search that finds an element in the list by searching the element sequentially until the element is found in the list.

Binary search-It is a search that finds the middle element in the list recursively until the middle element is matched with a searched element.

Digital output \(= \frac{{analog\ input}}{{resolution}}\)

\(= \frac{{8.73}}{{20mV}} = \frac{{\left( {873} \right)}}{2} = {\left( {436.5} \right)_{10}}\)

Since ADC outputs are purely integer values, the output of ADC is \({\left( {436} \right)_{10}}\)

Given, n = 12 bits

Clock period = 1 μs

Total conversion time = 14 μs

For successive approximation type ADC

T_C = n × clock period

= 12 × 1 μs = 12 μs ≈ 14 μs

The ADC must be successive approximation type

\({t_a} = {1 \over {{\rm{w}}\left( {{2^n} - 1} \right)}} = {1 \over {2{\rm{\pi }} \times 2 \times {{10}^3}\left( {{2^8} - 1} \right)}} = {\rm{ }}312{\rm{ }}\:ns\)