Flip-Flop MCQ Quiz - Objective Question with Answer for Flip-Flop - Download Free PDF

Concept: 

JK flip flop:

The truth table of JK flipflop:

T flip-flop is formed by combining both J and K inputs of the JK-flipflop

In the above truth table when J = K = 1, its output is toggled.

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Characteristic Table of JK flip flop

Qn+1 = JQ̅n + K̅Qn

The correct answer is: 1) Edge-triggering responds to the transition of the clock, while level-triggering responds to the level of the clock.

Triggering methods of flip-flop:

1.) Edge Triggering:

• In a sequential circuit, if the output changes when the signal transits from a high level to a low level or from a low level to a high level, we call it edge triggering. 
• Here, the edge that changes the voltage from the low level to the high level is called the positive edge.
• And, the edge that changes the voltage from the high level to the low level is called the negative edge.

2.) Level Triggering:

• In the sequential circuit, if the output changes during the high voltage period or low voltage period, it is called level triggering.
• The output of the circuit is high for a positive level and low for a negative level. 

The correct answer is Option 2: Gated D Latch.

Concept

Latches are basic building blocks in digital electronics that are used to store one bit of data. They are often used in memory devices, registers, and flip-flops. The output of a latch depends on the input signals and the enable signal.

In the given question, we are asked to identify which type of latch changes its output only when the enable signal is active and there is a change in the input.

 Additional Information

Option 1: D Latch

A D Latch, also known as a Data Latch, is a general term that can refer to both gated and non-gated versions. Without specifying "gated," it is ambiguous. The gated version (Gated D Latch) specifically matches the condition given in the question.

Option 2: Gated D Latch

A Gated D Latch changes its output based on the input only when the enable signal is active. This matches the condition given in the question, making it the correct answer.

Option 3: T Latch

A T Latch (Toggle Latch) changes its state (toggles) whenever the enable signal is high and the input (T) is 1. It does not directly follow the input, hence it does not match the condition given in the question.

Option 4: SR Latch

An SR Latch (Set-Reset Latch) changes its output based on the set (S) and reset (R) inputs. It does not have an enable signal that controls when the input changes are accepted, so it does not match the condition given in the question.

Concept

The characteristics equation of JK flip flop is:

\(Q_{n+1}=J\bar{Q_n}+\bar{K}Q_n\)

where, \({Q_{n+1}}=Next \space state\)

\(Q_n=Present \space state\)

Calculation

From the given figure, \(J=\bar{Q}\) and K = 1

\(Q_{n+1}=\bar{Q_n}\bar{Q_n}+\bar{1}Q_n\)

\(Q_{n+1}=\bar{Q_n}\)

The next stage is toggling for every clock pulse.

It is given that the flip-flop was initially cleared. So, Q_n = 0, so \(Q_{n+1}=\bar{0}=1\)

So, after 1^st clock pulse, the output will again toggle to 0.

After the 6^th clock pulse, the sequence of the output will be 010101.

Concept

The maximum propagation delay (t_pd) for the synchronous counter is given by:

t_pd = t_d

tpd = Propagation delay of 1 Flip flop

Calculation

Given is a 4-bit synchronous counter for which the maximum possible time needed for the change of state will be the maximum possible propagation delay:

t_pd = Delay of 1 flip-flop only

tpd = 25 ns 

Mistake Points

The maximum propagation delay (tpd) for an asynchronous counter is given by:

tpd = n × td 

tpd = Propagation delay of 1 Flip flop

n = No. of flip flops

Truth Table of J-K flip flop

At J = 0, K = 0, the J-K flip flop has no changes in the next state from the present state.

Truth Table of S-R flip flop

Truth Table of D flip flop

Truth Table of T flip flop

D flip flop:

D flip flop has only one input terminal. The output of the D flip flop will be the same as the input. Hence, it is used in delay circuits.

The circuit is as shown below.

Logic symbol:

Truth table:

Characteristic equation: Q_n+1 = D

The D flip flop may be obtained from an S-R flip flop by just putting one inverter between the S and R as shown in the figure below.

S = R̅

The D flip flop may be obtained from a J-K flip flop by just putting one inverter between the J and K as shown in the figure below.

K = J̅

T flip flop:

T flip flop has only one input terminal. The output of the T flip flop will be toggled when the input is high on every new clock pulse. The output will be the same as the previous state when the input is low.

The circuit is as shown below.

Logic symbol:

Truth table:

Characteristic equation: Q_n+1 = TQ̅­_n + T̅Q_n

The T flip flop may be obtained from a J-K flip flop by making both the inputs are the same i.e. J = K.

Flip-Flop

• A flip-flop is the basic storage element in sequential logic.
• A flip-flop is a device that stores a single bit (binary digit) of data.
• The stored data can be changed by applying varying inputs.
• Flip Flops are edge-triggered while the latch is level-triggered.
• Flip Flops are of 4 types: SR, JK, T, and D flip-flops.

​Register

• A Register is a collection of flip-flops.
• For storing n-bit data, a register comprising of n number of flip-flops is used.

GATE

• A logic gate is a device that acts as a building block for digital circuits.
• They perform basic logical functions that are fundamental to digital circuits. 
• Example: AND, OR, NOT, NAND, NOR, XOR, XNOR

Race around condition:

For JK flip-flop if J, K, and Clock are equal to 1 the state of flip-flop keeps on toggling which leads to uncertainty in determining the output of the flip-flop. This problem is called Race around the condition.

This can be eliminated by using the following methods.

• Increasing the delay of flip-flop
• Use of edge-triggered flip-flop
• Use of master-slave JK flip flop

The Master-slave configuration is used in a flipflop to eliminate the race around condition but not to store two bits of information.

D flip flop :

D flip flop has only one input terminal. The output of the D flip flop will be the same as the input. Hence, it is used in delay circuits.

The circuit is as shown below.

Logic symbol:

Truth table:

The D flip flop may be obtained from an S-R flip flop by just putting one inverter between the S and R as shown in the figure below.

S = R̅

∴ The one input RS flip flop is the D flip flop.

The PRESET and CLEAR inputs of the JK Flip-Flop are asynchronous, which means that they will have an immediate effect on the Q and Q’ outputs regardless of the state of the clock and / or the J and K inputs.

1.When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of the synchronous inputs or the clock.

 2.When the clear input is activated, the flip-flop will be reset (Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock.

3.When preset and clear inputs are activated we get an invalid state on the output, where Q and not-Q go to the same state.

Important Points-

JK Flip-Flop Truth Table- From  truth table it can be seen that the CLEAR (CLR) and PRESET inputs are active at a low logic level  and put on the Q output of the Flip-Flop, a high logic level regardless of the state of the clock and / or the state of the J and K inputs.

Concept:

D flip flop :

D flip flop has only one input terminal. The output of the D flip flop will be the same as the input. Hence, it is used in delay circuits.

The circuit is as shown below.

Logic symbol:

Truth table:

Important Points

The D flip flop may be obtained from an S-R flip flop by just putting one inverter between the S and R as shown in the figure below.

S = R̅

∴ The one input RS flip flop is the D flip flop.

The correct answer is One bit of data.

Key Points

• A flip-flop is a basic digital memory circuit, also known as a bistable multivibrator.
• It has two stable states, which can be used to store binary information.
• Each flip-flop can store exactly one bit of data, representing either a 0 or a 1.
• Flip-flops are fundamental building blocks of digital electronics systems used in computers, communications, and many other types of systems.`

1) All flipflops except D – FF have input conditions that drive them in the Hold state.

2) However D – FF does not have such an input condition. Output always follows the input.

Key Notes:

All flipflop truth tables are defined below:

SR flipflop

JK flipflop:

T flipflop:

The correct answer is option 4

Analysis:

Truth table for J-K flip flop:

So, the output will toggle when both the inputs are 1, i.e.

J = K = 1