Question
Download Solution PDFWhat is the process of designing more than 100 gates on a single chip?
Answer (Detailed Solution Below)
Detailed Solution
Download Solution PDFDifferent scales of integration and the number of components (logic gates) in them are:
|
Complexity |
Number of Gates (Components) |
|
Small-Scale Integration (SSI) |
< 12 |
|
Medium Scale Integration (MSI) |
12 to 99 |
|
Large Scale Integration (LSI) |
100 to 9999 |
|
Very Large Scale Integration (VLSI) |
10,000 to 99,999 |
|
Ultra Large Scale Integration (ULSI) |
100,000 to 999,999 |
Last updated on Feb 18, 2025
-> The RRB JE EC CBT 2 Exam Date has been released which will be conducted on 19th and 20th March 2025.
-> Earlier, RRB JE Electronics Engineer CBT 1 Answer Key has been released. The examination took place on 16th to 18th December 2024.
-> A total of 7911 vacancies have been announced for Junior Engineers. The distributed vacancy is yet to be announced. The application dates will also be announced soon.
-> This is a central government job and the selected candidates will get a salary according to the 7th pay commission's Level 6. The starting pay would be Rs.35,400, excluding all benefits.
-> The maximum age of the candidates should not exceed 33 years. The candidates must go through the RRB JE EC syllabus and exam pattern. They should not let this golden opportunity slip away from their hands.