In case of a monolithic phase-locked loop, the equation of free running frequency of the voltage controlled oscillator is

This question was previously asked in
UGC NET Paper 2: Electronic Science June 2019 Official Paper
View all UGC NET Papers >
  1. \({f_{out}} \cong \frac{{1.2\;}}{{2{R_1}{C_1}}}Hz,\)
  2. \({f_{out}} \cong \frac{{1.2\;}}{{{R_1}{C_1}}}Hz\)
  3. \({f_{out}} \cong \frac{{4\;}}{{1.2{R_1}{C_1}}}Hz\)
  4. \({f_{out}} \cong \frac{{1.2\;}}{{4{R_1}{C_1}}}Hz\)

Answer (Detailed Solution Below)

Option 4 : \({f_{out}} \cong \frac{{1.2\;}}{{4{R_1}{C_1}}}Hz\)
Free
UGC NET Paper 1: Held on 21st August 2024 Shift 1
16.1 K Users
50 Questions 100 Marks 60 Mins

Detailed Solution

Download Solution PDF

Phase-locked loop (PLL):

  • A phase-locked loop is a control system that generates an output signal whose phase is related to the phase of an input signal.
  • The circuit can track an input frequency or it can generate a frequency that is a multiple of the input frequency.
  • The basic elements of a PLL circuit are phase comparator/detector, a loop filter, voltage-controlled oscillator (VCO).

The figure shows a schematic of a phase-locked loop:

RRB JE EE 41 16Q AC Fundamentals 1 Hindi.docx 14

The center frequency of the PLL is determined by the free-running frequency of the VCO, which is given by:

\({f_{OUT}} = \frac{{1.2}}{{4{R_1}{C_1}}}Hz\)

R1 and C1 = External resistors and Capacitors

The VCO free-running frequency fout is adjusted externally with R1 and C1 to be at the center of the input frequency range.

The lock range fL and capture of PLL is given by:

\({f_L} = \; \pm \frac{{8{f_{OUT}}}}{V}Hz\)  

fOUT = Free-running frequency of VCO (Hz)

v = (+v) – (-v) volts

Latest UGC NET Updates

Last updated on Jun 27, 2025

-> Check out the UGC NET Answer key 2025 for the exams conducted from 25th June.

-> The UGC Net Admit Card has been released on its official website today.

-> The UGC NET June 2025 exam will be conducted from 25th to 29th June 2025.

-> The UGC-NET exam takes place for 85 subjects, to determine the eligibility for 'Junior Research Fellowship’ and ‘Assistant Professor’ posts, as well as for PhD. admissions.

-> The exam is conducted bi-annually - in June and December cycles.

-> The exam comprises two papers - Paper I and Paper II. Paper I consists of 50 questions and Paper II consists of 100 questions. 

-> The candidates who are preparing for the exam can check the UGC NET Previous Year Papers and UGC NET Test Series to boost their preparations.

More Frequency Modulation Questions

More Angle Modulation Questions

Get Free Access Now
Hot Links: teen patti cash teen patti game paisa wala teen patti real cash game teen patti download teen patti comfun card online