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A computer system has a 4 K word cache organized in a block-set associative manner with 4 blocks per set, 64 words per block. The numbers of bits in the SET and WORD fields of the main memory address formula are respectively:

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  1. 15 and 4
  2. 6 and 4
  3. 7 and 2
  4. 4 and 6

Answer (Detailed Solution Below)

Option 4 : 4 and 6
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\(\# \;blocks = \frac{{4K}}{{64}} = 64\) 

\(\# \;sets = \frac{{64}}{4} = 16\) 

⇒ 4 bits for SET

Each block has 64 words

⇒ 6-bits required for word.

Tag

Set

Word

 

(4)Bit

(6)Bit
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Q1.The size of the cache tag directory is
Q2.The number of bits in the tag field of an address is
Q3.A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the minimum number of page colours needed to guarantee that no two synonyms map to different sets in the processor cache of this computer?
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Q5.A computer system has a 4 K word cache organized in a block-set associative manner with 4 blocks per set, 64 words per block. The numbers of bits in the SET and WORD fields of the main memory address formula are respectively:
Q6.If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
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Q8.An access sequence of cache block addresses is of length N and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by k. What is the miss ratio it the access sequence is passed through a cache of associativity A ≥ k exercising least-recently-used replacement policy?
Q9.A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB. The number of bits for the TAG field is _____
Q10.The main memory of a computer has 2 cm blocks while the cache has 2c blocks. If cache uses set associative mapping scheme with two blocks per set, then the block k of the main memory maps to set:

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Q1.More than one word is put in one cache block to : 
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Q3.What is Cache memory?
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Q6.Indexed/grouped allocation is useful as : (A) It supports both sequential and direct access. (B) Entire block is available for data. (C) It does not require lots of space for keeping pointers. (D) No external fragmentation. Choose the correct answer from the options given below:
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Q1.Which of the following statement(s) is/are correct? Statement A : ALU can perform both arithmetic and logical operations. Statement B : CPU is used to process, display and store data or information.
Q2.The addressing mode/s, which uses the PC instead of a general-purpose register is : 
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